// *************************************************************************
// IVe-NOTE : REQUIRED : Design top file : 07 Example - DUT
// -------------------------------------------------------------------------
// Use this section to define an example DUT for your UVe.
// To do so replace the following DUT skeleton with an actual DUT.
// If you choose to replace this file, or rename it, you should update the
// example config file and demo file accordingly.


// Environment constants
`define AHB_DATA_WIDTH          32              // AHB bus data width 
`define AHB_ADDR_WIDTH          32              // AHB bus address width [32/64]
`define AHB_DATA_MAX_BIT        31              // MUST BE: AHB_DATA_WIDTH - 1
`define AHB_ADDRESS_MAX_BIT     31              // MUST BE: AHB_ADDR_WIDTH - 1


//`define DEFAULT_HREADY_VALUE    1'b1                    // Ready Asserted
//`define DEFAULT_HRESP_VALUE     1'b0                   // OKAY Response
//`define DEFAULT_HRDATA_VALUE    {`AHB_DATA_WIDTH{1'b0}} // All zeros

module vv_ahblite_mux(//out
							hready, hresp, hrdata,
							//in
							hready0 ,hresp0, hrdata0 ,
							hready1 ,hresp1, hrdata1 ,
							hready2 ,hresp2, hrdata2 ,
							hready3 ,hresp3, hrdata3,
							hsel0,hsel1,hsel2,hsel3,
							//
							clock,reset_n);
   // AHB Slave Pre-Multiplexed Signals

output hready; 
output hresp;
output [`AHB_DATA_MAX_BIT:0] hrdata;

input  hready0 , hready1 , hready2 , hready3 ;
input  		 hresp0 , hresp1 , hresp2 , hresp3 ;
input  [`AHB_DATA_MAX_BIT:0] hrdata0 , hrdata1 , hrdata2 , hrdata3 ;
input hsel0 , hsel1 , hsel2 , hsel3;
    
input reset_n;
input clock;  
    
wire   hready0 , hready1 , hready2 , hready3 ;
wire   hresp0 , hresp1 , hresp2 , hresp3 ;  
wire   [`AHB_DATA_MAX_BIT:0] hrdata0 , hrdata1 , hrdata2 , hrdata3 ;

wire   reset_n;
wire   clock;
  
reg       hready;
reg 		 hresp; 
reg [`AHB_DATA_MAX_BIT:0]  hrdata;
  
reg [3:0] sel_reg;
   //------------------------------------------------------
   always @ ( posedge clock )
    begin : DATA_MUX_CONTROL
      
      if ( reset_n == 1'b0 )
      begin
	     // sel_reg <= 4'b0000;    
	     sel_reg <= { hsel3,  hsel2,  hsel1,  hsel0 };
      end // if ( !hreset_n )
     else
      if ( hready == 1'b1 )
      begin
      	sel_reg <= { hsel3,  hsel2,  hsel1,  hsel0 };
      end // if ( hready )
    end // block: DATA_MUX_CONTROL
    
   //------------------------------------------------------
   always @ ( hready0  or hready1  or hready2  or hready3 or
	     		hresp0  or hresp1  or hresp2  or hresp3  or
	     		hrdata0  or hrdata1  or hrdata2  or hrdata3  or	     
	     		sel_reg )  
   begin : SLAVE_RESPONSE_MUX
	
    case ( sel_reg )
          
      4'b1000 : begin 
	
		hready <= hready3;
		hresp  <= hresp3;
		hrdata <= hrdata3;
	
      end // case: 4'b1000
      
      4'b0100 : begin

		hready <= hready2;
		hresp  <= hresp2;
		hrdata <= hrdata2;
	
      end // case: 4'b0100
      
      4'b0010 : begin 
	
		hready <= hready1;
		hresp  <= hresp1;
		hrdata <= hrdata1;

      end // case: 4'b0010
      
      4'b0001 : begin
	
		hready <= hready0;
		hresp  <= hresp0;
     	hrdata <= hrdata0;

      end // case: 4'b0001
      
      default  : begin
	
	  hready <= `DEFAULT_HREADY_VALUE;
	  hresp  <= `DEFAULT_HRESP_VALUE;
	  hrdata <= `DEFAULT_HRDATA_VALUE;
	
      end // case: default
      
    endcase // case( sel_reg )
  end // block: RESPONSE_MUX
   
endmodule

// *************************************************************************


